1/10 sta508 february 2006 1features multipower bcd technology minimum input output pulse width distortion 200m ? r dson complementary dmos output stage cmos compatible logic inputs thermal protection thermal warning output under voltage protection 2 description sta508 is a monolithic quad half bridge stage in mul- tipower bcd technology. the device can be used as dual bridge or reconfigured, by connecting config pin to vdd pin, as single bridge with double current capability, and as half bridge (binary mode) with half current capability. the device is particularly designed to make the out- put stage of a stereo all-digital high efficiency (ddx?) amplifier capable to deliver 80 + 80w @ thd = 10% at v cc 35v output power on 8 ? load. in single btl configuration is also capable to deliver a peak of 160w @thd = 10% at v cc = 35v on 4 ? load. the input pins have threshold proportional to v l pin voltage. 40v 4.5a quad power half bridge figure 2. block diagram l18 22 h l19 22 h c30 1 f c20 100nf c99 100nf c101 100nf c107 100nf c106 100nf c23 470nf c55 1000 f c21 100nf c58 100nf c58 100nf r57 10k r59 10k r63 20 r98 6 r100 6 c53 100nf c60 100nf c31 1 f c52 330pf r104 20 c109 330pf 15 m3 in1a in1a v l config pwrdn pwrdn fault tri-state th_war th_war +3.3v in1b v dd v dd v ss v ss v cc sign v cc sign gnd-reg gnd-clean in2a in1b in2a in2b protections & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m5 m4 17 16 out1a gnd1a out1a v cc 1a 14 12 10 11 out1b gnd1b out1b v cc 1b 13 l113 22 h l112 22 h c32 1 f +v cc c108 470nf c33 1 f 7 m17 m15 m16 m14 8 9 out2a gnd2a out2a v cc 2a 6 4 2 3 out2b gnd2b d00au1148b out2b v cc 2b 5 19 31 20 gndsub 1 in2b 32 c110 100nf c111 100nf r103 6 r102 6 8 ? 8 ? rev. 4 fi gure 1. p ac k age table 1. order codes part number package sta508 powerso36 powerso36
sta508 2/10 table 2. pin description n pin description 1 gnd-sub substrate ground 2 ; 3 out2b output half bridge 2b 4v cc 2b positive supply 5 gnd2b negative supply 6 gnd2a negative supply 7v cc 2a positive supply 8 ; 9 out2a output half bridge 2a 10 ; 11 out1b output half bridge 1b 12 v cc 1b positive supply 13 gnd1b negative supply 14 gnd1a negative supply 15 v cc 1a positive supply 16 ; 17 out1a output half bridge 1a 18 nc not connected 19 gnd-clean logical ground 20 gnd-reg ground for regulator v dd 21 ; 22 v dd 5v regulator referred to ground 23 v l high logical state setting voltage 24 config configuration pin 25 pwrdn stand-by pin 26 tri-state hi-z pin 27 fault fault pin advisor 28 th-war thermal warning advisor 29 in1a input of half bridge 1a 30 in1b input of half bridge 1b 31 in2a input of half bridge 2a 32 in2b input of half bridge 2b 33 ; 34 v ss 5v regulator referred to +v cc 35 ; 36 v cc sign signal positive supply
3/10 sta508 table 3. functional pin status (*) : the pin is open collector. to have the high logic value, it needs to be pulled up by a resistor. (**): to put config = 1 means connect pin 24 (config) to pins 21, 22 (vdd) figure 3. pin connection table 4. thermal data pin name logical value ic -status fault 0 fault detected (short circuit, or thermal ..) fault (*) 1 normal operation tri-state 0 all powers in hi-z state tri-state 1 normal operation pwrdn 0 low absorpion pwrdn 1 normal operation thwar 0 temperature of the ic =130c thwar (*) 1 normal operation config 0 normal operation config (**) 1 out1a = out1b ; out2a=out2b (if in1a = in1b; in2a = in2b) symbol description value unit r th j-case thermal resistance junction-case max 1.5 c/w gnd-sub out2b out2b v cc 2b gnd1b v cc 1a gnd1a out1a out1a gnd-reg v dd v dd config v ss v ss v cc sign v cc sign 18 16 17 15 6 5 4 3 2 21 22 31 32 33 35 34 36 20 1 19 n.c. gnd-clean d01au1273 out1b v cc 1b out1b pwrdn fault tri-state 9 8 7 28 29 30 out2a th_war 10 27 gnd2b out2a v cc 2a in1a in2b in1b 14 12 11 23 25 26 gnd2a in2a 13 24 v l
sta508 4/10 table 5. absolute maximum ratings table 6. electrical characteristcs (v l = 3.3v; v cc = 30v; t amb = 25c ; f sw =384 unless otherwise specified) symbol parameter value unit v cc dc supply voltage (pin 4,7,12,15) 40 v v max maximum voltage on pins 23 to 32 5.5 v p tot power dissipation (t case = 70c) 50 w t op operating temperature range -40 to 90 c t stg , t j storage and junction temperature -40 to 150 c symbol parameter test conditions min. typ. max. unit r dson power pchannel/nchannel mosfet rdson id=1a 200 270 m ? i dss power pchannel/nchannel leakage idss v cc =35v 50 a g n power pchannel rdson matching id=1a 95 % g p power nchannel rdson matching id=1a 95 % dt_s low current dead time (static) see test circuit no.1; see fig. 4 10 20 ns dt_d high current dead time (dinamic) l=22 h; c = 470nf; r l = 8 ? id=3.5a; see fig. 3 50 ns t d on turn-on delay time resistive load 100 ns t d off turn-off delay time resistive load 100 ns t r rise time resistive load; as fig.4 25 ns t f fall time resistive load; as fig. 4 25 ns v cc supply voltage operating voltage 10 36 v v in-high high level input voltage v l /2 +300mv v v in-low low level input voltage v l /2 - 300mv v i in-high high level input current pin voltage = v l 1 a i in-low low level input current pin voltage = 0.3v 1 a i pwrdn-h high level pwrdn pin input current v l = 3.3v 35 a v l low logical state voltage vl (pin pwrdn, tristate) (note 1) v l = 3.3v 0.8 v
5/10 sta508 table 7. notes: 1. the following table explains the vlow, vhigh variation with v l note 2: see relevant application note an1994 table 8. logic truth table (see fig. 5) v h high logical state voltage vh (pin pwrdn, tristate) (note 1) v l = 3.3v 1.7 v i vcc- pwrdn supply current from vcc in power down pwrdn = 0 3 ma i fault output current pins fault -th-warn when fault conditions vpin = 3.3v 1 ma i vcc-hiz supply current from vcc in tri- state v cc = 30v; tri-state = 0 22 ma i vcc supply current from vcc in operation both channel switching) v cc =30v; input pulse width = 50% duty; switching frequency = 384khz; no lc filters; 50 ma i vcc-q isc (short circuit current limit) (note 2) 4.5 6 9 a v uv undervoltage protection threshold 7 v t pw-min output minimum pulse width no load 70 150 ns v l vlow min vhigh max unit 2.7 0.7 1.5 v 3.3 0.8 1.7 v 5 0.85 1.85 v tri-state inxa inxb q1 q2 q3 q4 output mode 0xxoffoffoffoffhi-z 1 0 0 off off on on dump 101offononoffnegative 1 1 0 on off off on positive 1 1 1 on on off off not used symbol parameter test conditions min. typ. max. unit table 6. electrical characteristcs (continued)
sta508 6/10 figure 4. test circuit. figure 5. figure 6. low current dead time = max(dtr,dtf) outxy vcc (3/4)vcc (1/2)vcc (1/4)vcc t dtf dtr duty cycle = 50% inxy outxy gnd +vcc m58 m57 r 8 ? + - v67 = vdc = vcc/2 d03au1458 inxa inxb +v cc q1 q3 q2 q4 outxa gnd outxb d00au1134 high current dead time for bridge application = abs(dtout(a)-dtin(a))+abs(dtout(b)-dtin(b)) +v cc rload=8 ? q2 outb dtout(b) dtin(b) dtout(a) c71 470nf c70 470nf c69 470nf iout=4a iout=4a q4 q1 q3 m64 inb m63 d03au1517 m58 ina m57 dtin(a) duty cycle=a duty cycle=b duty cycle a and b: fixed to have dc output current of 4a in the direction shown in figure l68 22 l67 22 outa
7/10 sta508 figure 7. typical single btl configuration figure 8. typical quad half bridge configuration for more information refer to the application notes an1456 and an1661 10 h 10 h 100nf film 100nf x7r 100nf x7r 1 f x7r 2200 f 63v 470nf film 100nf film 100nf 10k 10k 6.2 1/2w 6.2 1/2w 100nf x7r 100nf x7r add. in1a in1a v l config pwrdn npwrdn fault tri-state th_war th_war +3.3v 100nf 100nf x7r in1b v dd v dd v ss v ss v cc sign v cc sign gnd-reg gnd-clean in1b in2a 29 23 n.c. 24 25 27 26 28 30 21 22 33 34 35 36 17 16 18 out1a gnd1b out1a v cc 1b 10 13 11 out1b gnd1a out1b 14 32v 330pf 22 ? 1/2w 4 ? gnd2a 6 2 12 v cc 1a 15 v cc 2b 4 v cc 2a 7 3 out2b gnd2b d03au1514 out2b 5 19 31 20 gndsub 1 in2b 32 8 9 out2a out2a 1 f x7r 32v l11 22 h l12 22 h c51 1 f c71 100nf c91 1 f c81 100nf c31 820 f c21 2200 f c58 100nf c58 100nf r57 10k r59 10k r41 20 r61 5k r62 5k r51 6 c53 100nf c60 100nf c61 100nf 15 m3 in1a in1a vl config pwrdn pwrdn fault tri-state th_war th_war +3.3v in1b v dd v dd v ss v ss v cc sign v cc sign gnd-reg gnd-clean in2a in1b in2a in2b protections & logic regulators 29 23 24 25 27 26 28 30 21 22 33 34 35 36 m2 m5 m4 17 16 outpl pgnd1p outpl v cc 1p 14 12 10 11 outnl pgnd1n outnl v cc 1n 13 c52 1 f +v cc c62 100nf 7 m17 m15 m16 m14 8 9 outpr pgnd2p outpr v cc 2p 6 4 2 3 outnr pgnd2n d03au1474 outnr v cc 2n 5 19 31 20 gndsub 1 in2b 32 c72 100nf c92 1 f c82 100nf r52 6 c41 330pf r42 20 c42 330pf c32 820 f l13 22 h l14 22 h c73 100nf c93 1 f c83 100nf c33 820 f r43 20 r53 6 c74 100nf c94 1 f c84 100nf r54 6 c43 330pf r44 20 c44 330pf c34 820 f r63 5k r64 5k r65 5k r66 5k r67 5k r68 5k 4 ? 4 ? 4 ? 4 ?
sta508 8/10 figure 9. power so36 (slug up) mechanical data & package dimensions outline and mechanical data m. mm inch min. typ. max. min. typ. max. a 3.25 3.43 0.128 0.135 a2 3.1 3.2 0.122 0.126 a4 0.8 1 0.031 0.039 a5 0.2 0.008 a1 0.030 -0.040 0.0011 -0.0015 b 0.22 0.38 0.008 0.015 c 0.23 0.32 0.009 0.012 d 15.8 16 0.622 0.630 d1 9.4 9.8 0.37 0.38 d2 1 0.039 e 13.9 14.5 0.547 0.57 e1 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 e4 2.9 3.2 0.114 1.259 e0.65 0.026 e3 11.05 0.435 g 0 0.075 0 0.003 h 15.5 15.9 0.61 0.625 h 1.1 0.043 l 0.8 1.1 0.031 0.043 n 10? 10? s8?8? (1) ?d and e1? do not include mold flash or protusions. mold flash or protusions shall not exceed 0.15mm (0.006?) (2) no intrusion allowed inwards the leads. di powerso36 (slug up) 7183931 d
9/10 sta508 table 9. revision history date revision description of changes september 1994 1 first issue june 2004 2 note 2: see relevant application note an1994 november 2004 3 changed vcc from 9 min to 10 min february 2006 4 changed t op value on table 5.
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